Complex devices, like “System on chip” (SoC) devices, have various functions like Logic, Analog, Power management and Memory. An interface to other external units these feature blocks can be connected to multiple device pins. For other components (e.g., DRAMS or Power IC's), such connections can be in the center of the die. Specially for high pin count devices like Logic or SoC, peripheral pads are also used. A chip having wire bond contacts needs supply terminals (supply pads) at an edge of the chip (in the so-called pad ring). In contrast to this, in the performance optimized integration of the voltage supply using the chip contact technology (“flip chip”) the terminals for the voltage supply can be arranged out of the pad ring in an inner area of the chip, preferably at the power grit.
For using a semiconductor die for flip chip technology (e.g., for use in a BGA-Ball Grid Array package) and wire bond technology (e.g., for use in a QFP-Quad Flat Package), the area of the supply pads in the pad ring used in wire bond technology can not be used for I/O pads in the flip chip technology.
As an example, using this area for additional I/O pads or reducing the size of the pad ring, and therefore the size of a chip (e.g., by moving the supply pads out of the pad ring to a center of the semiconductor chip), leads to the problem that the silicon can no longer be used for wire bonding, e.g., in QFP packages.